NETLIST, INC. v. MICRON TECHNOLOGY, INC.

Authored by: Jeremy J. Gustrowsky

The Federal Circuit affirmed a Patent Trial and Appeal Board decision holding every challenged claim of Netlist’s U.S. Patent No. 10,949,339 unpatentable as obvious. The patent covers computer memory modules, specifically ways to improve the performance and capacity of boards that use dual in-line memory modules. The design adds “buffers” between the memory controller and the dynamic random access memory (DRAM) chips. Those buffers contain data paths that stay switched off by default, electrically isolating the memory chips, and are turned on only when data actually needs to move during a read or write operation.

Samsung filed the original inter partes review petition, arguing that claims 1 through 35 were obvious in light of U.S. Patent Application Publication No. 2006/0277355 (“Ellsberry”) and U.S. Patent No. 7,024,518 (“Halbert”). Micron filed its own petition raising the same prior art and was joined as a petitioner. Samsung later settled with Netlist and dropped out, leaving Micron to defend the win on appeal. Everyone treated claim 1 as representative, and the dispute narrowed to two requirements: that a data path through the buffer be “enabled” so write data can be driven to the DRAM devices, and that the path be enabled at a particular moment (“in accordance with a latency parameter”) for a particular duration (a “first time period”).

On the timing requirement, Netlist argued the Board simply speculated that Ellsberry’s buffers (called “switch ASICs”) use a latency value known as Posted CAS to control when data paths open. Netlist insisted that value was merely passed through the buffer on its way to the memory chips. The Federal Circuit disagreed, pointing to Ellsberry’s disclosure that certain initialization commands, including the Posted CAS parameter, are sent to and stored in the memory bank switch rather than forwarded to the memory devices. The Board also relied on Ellsberry’s stated compatibility with JEDEC standards, where read and write latencies depend on Posted CAS latency. That was enough to qualify as substantial evidence.

The most interesting wrinkle involved a reference that was never part of the petition. To explain how a skilled engineer would account for the extra delay introduced by a buffer, the Board cited Netlist’s own U.S. Patent No. 7,532,537 and its teaching of adding one clock cycle for propagation delay. Netlist argued this transformed a document offered as background knowledge into a full-blown prior art reference, which would run afoul of the rule that the Board cannot invalidate claims on a combination of its own design rather than the one the petitioner presented. The Federal Circuit sidestepped the question entirely. Because the Board separately found that Ellsberry itself teaches adding a clock cycle to cover delay through its switch ASICs, supported by expert deposition testimony about a note in Ellsberry’s Figure 8B, any possible misstep was harmless. The court never had to decide whether the line was crossed.

Netlist fared no better on the “enabling a data path” requirement. It submitted a color-annotated version of Ellsberry’s Figure 2 to argue that the reference’s Ports A and B sit outside the buffer, so turning them on cannot be the same as opening a data path inside the buffer. The Board called that reading “manifestly incorrect,” and the Federal Circuit agreed. Ellsberry expressly states that the memory bank switch “includes Port A and Port B,” and the figure shows the ports as distinct from the memory banks. The Board also credited expert testimony that bidirectional drivers inside the switch are what open and close the data paths. Notably, Netlist never engaged with the Board’s backup finding that Halbert’s tristate buffers plainly have the ability to enable and disable data paths, a finding the court likewise held was supported by the record.

Netlist’s remaining arguments under the Administrative Procedure Act also failed. A two-sentence complaint that the Board resolved most limitations by merely summarizing the petitioner’s contentions and noting Netlist “does not dispute” them went nowhere, because Netlist never identified which limitations it meant. An appellate argument must be adequately developed to be considered. As for dependent claims 7, 16, and 21, the court walked through the Board’s findings and concluded the agency had in fact addressed Netlist’s points. Those claims require only that the module control signals operate in accordance with the latency parameter, not that the signals carry the parameter itself. Because the Board’s reasoning could be reasonably traced, there was no APA problem.

The practical lesson here is about redundancy and diligence. The Board’s decision survived a genuine question about whether it strayed beyond the petition, purely because it had articulated an independent basis for the same finding. Equally important, a patent owner who leaves an alternative ground unchallenged on appeal effectively concedes it. Costs were awarded against Netlist.